Meta's Production Use of Google Chips Signals a Major Shift in AI Infrastructure
The integration of Google's TPUs into Meta's core operations marks a historic departure from Nvidia's dominance in the AI hardware market.
By Chinedu Okafor ·

Google's custom tensor processing units are now operating in production environments at Meta, a development that marks the first time these chips have been sold to an external customer for large scale deployment. This move represents a significant structural change in the artificial intelligence infrastructure market, as it demonstrates that hyperscalers are actively diversifying their hardware portfolios beyond the traditional standards. The announcement, made on Google's developer blog, confirms that the hardware is no longer just a theoretical alternative but a live component of major tech operations.
The operational shift relies on a new PyTorch native version of the SGLang inference engine, which allows the hardware to function without requiring extensive code rewrites. Previously, running these chips required the use of Google's proprietary JAX framework, a barrier that kept many developers away. By creating a native bridge for PyTorch, the industry's dominant framework, the new tooling makes the chips a viable option for a much broader set of workloads. Meta's PyTorch TPU lead, Zongwei Zhou, described the result as a remarkably mature serving stack, noting that the outcome was the product of a close three way collaboration between Meta, Google, and the SGLang team.
Jana van Greunen, director of PyTorch engineering at Meta, emphasized that the company cannot be constrained by a single hardware architecture. She stated that the new TorchTPU system enables the deployment of PyTorch workloads directly onto Google's hardware. This strategic flexibility is crucial for Meta, which previously relied on an older bridge known as PyTorch XLA. Google has labeled that older tool a predecessor to the new system, while industry reports suggest that Meta research teams used TPUs through that bridge between 2020 and 2023 before canceling those specific contracts.
The commercial terms of this partnership remain partially opaque, with details on the physical location of the chips still unclear. However, prior reports indicated that discussions last year focused on Google Cloud TPU rentals for 2026, with potential purchases slated for 2027. It is now understood that Meta signed a multi year rental agreement, suggesting a long term commitment to the technology. This follows a similar move by Amazon, which announced the open sourcing of TorchNeuron for its own chips just one day prior at the same conference, indicating a coordinated industry effort to loosen software lock in.
Performance metrics suggest the new setup is highly competitive. A tuned version of the vLLM engine reportedly achieved over 700 tokens per second for a single user on the seventh generation Ironwood TPU. This figure surpasses the 452 tokens per second recorded on Nvidia's GB200 hardware during a comparable test. The speed increase is attributed to the use of speculative decoding, a method that accelerates inference using a smaller draft model. Additionally, the new kernels for specific models deliver roughly 1.4 to 2 times the baseline throughput at small batch sizes.
The ecosystem around this new stack is expanding rapidly. The SGLang team plans to add support for more models, starting with DeepSeek V4.1 Flash and Reflection Beam. They are also targeting day zero support for new open models by the first quarter of 2027. Stakeholders including Google, Meta, and RadixArk, the startup behind SGLang, will share further details at the SGLang Summit 2026 in San Francisco in November.
This development underscores the growing pressure on Nvidia to maintain its market position. As other major players build native connections to alternative silicon, the cost and complexity of switching hardware are decreasing. For investors and market analysts, the signal is clear: the AI hardware landscape is becoming more competitive, with software compatibility playing a central role in determining which chips gain traction in the enterprise.
Source: Tom's Hardware





